HOURS: Full-time, 40 hours per week SALARY: $143,874-$190,300 per year EMPLOYER: Semtech Corporation JOBSITE: 2580 North First Street, Suite 500 San Jose, CA 95131 Job Duties: Perform engineering duties related to specialized semiconductor packaging, manufacturing, and assembly processes for Semtech protection business unit products to meet performance and cost goals. Research, develop, and coordinate wafer-level semiconductor assembly manufacturing processes for new products, such as reviewing product qualifications, applying Design of Experiments (DoE) and statistical analysis to determine cause-and-effect relationships between factors and the output of a process, and resolving process issues. Provide package development support to the protection business unit throughout Semtech and customer applications support for new packages and hands-on package development, using knowledge of Computer Aided Design (CAD), such as AutoCAD. Develop and execute packaging qualification plans, document testing results, and identify opportunities to improve the overall packaging process including reducing cycle times, process capability improvements, and cost reductions. Characterize assembly manufacturing process with Failure Mode Effects Analysis (FMEA) and Finite Element Analysis (FEA) for product process development and to ensure reliability and robust manufacturing. Lead new package technology development initiatives, including wafer-level packaging from concept to full technology qualification. Conduct reliability analysis, failure analysis, and thermo-mechanical simulation in the design of microelectronic packages for automotive, industrial, and consumer electronics applications. Optimize new and current packaging processes by employing Statistical Process Control (SPC) and lean six sigma tools (Minitab), and perform root cause analysis for product and customer issues. Perform semiconductor packaging design and analysis from a production stand point for New Product Introduction (NPI). Provide support for sustaining production issues, and implement tracking methods for new products in packaging process. Monitor and oversee package qualification procedures with quality and reliability group, and recommend assembly design modifications to optimize system performance. Collaborate with marketing and applications team to create and implement packaging schematics, processes, and packaging design rules for new packages. Domestic and international travel to supplier sites to provide technical support and collect information for future roadmap products. May work several days per week remotely from home (within San Francisco Bay area). Schedule subject to manager approval. Requirements: 1. Masters degree in Industrial/Manufacturing Engineering, Mechanical Engineering, or related engineering field, and 8 years of experience as a Packaging Design Engineer, Process Engineer, or related engineering occupation in the semiconductor industry. OR Bachelors degree in Industrial/Manufacturing Engineering, Mechanical Engineering, or related engineering field, and 10 years of post-baccalaureate, progressive experience as a Packaging Design Engineer, Process Engineer, or related engineering occupation in the semiconductor industry. 2. Must have experience with the following: - Semiconductor Assembly Processes - Statistical Process Control (SPC) - Statistical Analysis - Thermo-mechanical Simulation - Computer Aided Design (CAD), including AutoCAD - Design of Experiments (DoE) - Failure Mode Effects Analysis (FMEA) - Reliability Analysis and Failure Analysis - Finite Element Analysis (FEA) - New Product Introduction (NPI) - Minitab 3. Domestic and international travel (United States, Asia) to supplier sites (up to 20%). HYBRID REMOTE: May work several days per week remotely from home (within San Francisco Bay area). Schedule subject to manager approval. To Apply, Email Resume to: Attn: P.Venkatathatham/RE: PPE